Experiences

Education Experiences

• Master of Science (Computer Science and Technology)
  🏫 Fudan University, Sep. 2022 - Jun. 2025
• Bachelor of Science (Elite Program in Computer Science and Technology)
  🏫 Fudan University, Sep. 2018 - Jun. 2022

Work Experiences

• Research Intern (In Progress)
  🏢 Shenzhen Institute of Computing Sciences, Dec. 2023 - Now
  Doing researches in data quality (data cleaning), vector DB, etc.
• Platform Engineering Intern
  ☁️ Alibaba Cloud (China), Jun. 2021 - Sep. 2021
  Exploring high-performance network packet processing techniques (XDP and DPDK).

Research Experiences

• Data Quality & Data Cleaning (In Progress)
  🏢 Shenzhen Institute of Computing Sciences, Dec. 2023 - Now
  Collaborated with Prof. Wenfei Fan and Dr. Weilong Ren
  • To be submitted.
  • Doing researches on how to clean the data better.

• Akane: Perplexity-Guided Time Series Data Cleaning
  🏫 Fudan University, Apr. 2023 - Jan. 2024
  Collaborated with Prof. Zhenying He and Prof. Peng Wang
  • Accepted to SIGMOD 2024. 🎉
  • Analogize recurrent patterns in the time series data to the word combinations in the textual data.
  • Formalize the data cleaning problem as minimizing the perplexity of the time series.
  • Design a four-phase framework Akane to solve the problem, and further propose advanced solutions.
  • Conduct experiments with 11 baselines on 12 real-world datasets to prove superiority.

• RpDelta: Supporting UCR-Suite on Multi-Versioning Time Series Data
  🏫 Fudan University, Feb. 2022 - Dec. 2022
  Collaborated with Prof. Zhenying He
  • Accepted to DASFAA 2023. 🎉
  • Focus on the issues of multi-versioning time series data arising from various cleaning algorithms.
  • Design an efficient storage strategy RpDelta.
  • Transplant the subsequence matching algorithm UCR-Suite on it.
  • Conduct Experiments on UCR Time Series Classification Archive Dataset.

Contest Experiences

• "Loongson Cup" National Student Computer System Capability Challenge
  🏫 Fudan University, Jun. 2020 - Aug. 2020
  Collaborated with Prof. Liang Zhang and Dr. Chen Chen
  • Wining the Second Prize Domestically (6th place). 🎉
  • Be a project leader of a four-person team with members Xiaoyu Han, Fanqi Yu, Weichen Li, and Yijun Ma.
  • Implement an experimental dual-issued MIPS CPU using System Verilog.
  • Incorporate memory hierarchy design for optimization (~30x faster) with great compatibility.
  • Burn the implemented CPU into an FPGA and initiating PMON (similar to BIOS) on it